#综合脚本
set top_module riscv_npu_soc
read_verilog {riscv_npu_top.sv npu_dotp_relu.sv rv32im_core.sv bram_4kx32.sv jtag_tap.sv apb_debug_port.sv axi_interconnect_1x2.sv}
link_design $top_module
compile_ultra -gate_clock -no_autoungroup
write -f verilog -hierarchy -output ${top_module}_syn.v
write_sdc ${top_module}_syn.sdc
report_area > area.rpt
report_timing > timing.rpt
report_power > power.rpt